Method and circuit arrangement for memory error processing

ABSTRACT

The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

The present invention relates to a method and circuit arrangement forperforming an error processing in a memory arrangement with a redundancysystem.

From the very early stages of memory development, designers haverecognized the need for some sort of on-chip error recovery circuitry.That is, given the large number of processing steps needed to make amemory chip, and given the large number of discrete memory cells to befabricated, from a practical standpoint it is inevitable that at leastsome memory cells will not function properly.

One of the first on-chip error recovery techniques utilized in theindustry was the general idea of redundancy. In redundancy, one or morespare lines of cells are added to the chip. These can be either spareword lines or spare bit lines. Typically, a standard address decoder isprovided for each redundant line. After the memory chip is manufactured,it is tested to determine the address of faulty memory cells. Theseaddresses are programmed into the address decoder for the redundantlines, by using any kind of non-volatile memory. When an externaladdress is supplied to the memory chip for a line on which the faultycell resides, the address decoder for the redundant lines activates aredundant line instead of the line comprising the faulty memory cell. Inthis manner, if discrete cells in the memory chip are inoperative,redundant cells can be substituted for them. Such redundancy systems aredescribed e.g. in the U.S. Pat. No. 3,753,244 and the U.S. Pat. No.3,755,791.

FIG. 2 shows a circuit arrangement for a memory error recovery similarto the above redundancy system, where non-volatile elements (NVE) 10such as fuses or a flash memory, are arranged to store the faultyaddresses. The setting or writing of the NVE 10 is done after testingthe concerned memory. During an operational mode, an initializationperiod is used to read the faulty-address information and to store it ina volatile storage and compare unit (VSC) 20. The VSC 20 may compriselatches, flip flops or an SRAM (Static Random Access Memory) memory.Thereby, the faulty-address information is always available and can becompared with externally applied addresses. The transfer of thefaulty-address information from the NVE 10 to the VSC 20 is done forvarious reasons. On the one hand, it is time-consuming to read the NVE10 at every addressing and then compare the read faulty-addressinformation with the externally applied addresses. On the other hand,the power consumption may be increased due to high-reading currentsrequired if resistive fuses or the like are used in the NVE 10.Generally, it is desired that the external addresses are compared withthe faulty-address information by a very fast procedure which can beachieved by using a volatile memory in the VSC 20.

In the arrangement shown in FIG. 2, the addressing of the memory isperformed as follows. A redundant memory portion for four faultyaddresses of 8 bits is provided. Thus, 32 bits need to be stored in theNVE 10, which are read and stored in the VSC 20. An externally appliedaddress A_(ext) of 8 bits is supplied to the VSC 20. The externaladdress (e.g. A0–A7) is compared with four series of bits (bit numbers0–7, 8–15, 16–23 and 24–31) of the VSC 20, which correspond to theavailable faulty addresses. If all 8 address bits of the externaladdress A_(ext) match with one of the bit series stored in the VSC 20, aredundant row in the redundant portion of the addressed memory isactivated by issuing one of the signals RR0–RR3. In this case, thenormal row decoder will be unselected or deactivated, such that the rowcomprising the faulty cell is not addressed. This can be done by issuinga corresponding signal to the address decoder of the addressed memory.

However, even the faulty-address information stored in the VSC 20, canbe subject to all kinds of errors which could change the state of onefaulty-address bit. This may lead to severe consequences for thefunctionality of the system.

It is therefore an object of the present invention to provide a methodand circuit arrangement for memory error correction, by means of whichreliability of the employed redundancy system can be increased.

This object is achieved by a method as defined in claim 1 and by acircuit arrangement as defined in claim 7.

According to the invention, a redundancy is added to the address of afaulty cell during the recording or storing thereof. Then, an errorprocessing for detecting or correcting an error is applied to the storedaddress before comparing it to an external or run time address. Thus,errors due to faulty redundancy addresses can be prevented.

In the circuit arrangement, an error processing circuit is added to theredundancy system between the volatile memory of the faulty-addressinformation and the comparing function of the faulty-address informationwith the externally applied addresses. Thus, at least one additional bitis needed to introduce the required redundancy in the non-volatileelements and also in the volatile memory for the faulty-addressinformation. When a bit of the faulty-address information in thevolatile memory or the non-volatile memory is changed due to an errore.g. an alpha particle or the like, the error processing circuit willcorrect or at least detect this failure and the system will continue tofunction.

Preferably, the error processing is an error correction processing.Thus, the amount of redundancy added to the faulty-address informationis selected so as to enable a correction of a detected error. The codingmay be any kind of error correction coding which enables a directcorrection of a detected error.

The faulty-address information may be read from a non-volatile memoryand stored in a volatile memory at an initialization procedure.

The redundancy may be added by adding a predetermined number of errorcorrection code bits to the faulty-address information.

Furthermore, the error processing step may comprise a decoding step fordecoding the coded faulty-address information.

Preferably, the volatile memory may be a latch, flip flop or SRAMmemory. The non-volatile memory may be a fuse, antifuse or flash memory,an EPROM (Erasable Programmable Read Only Memory), an EEPROM(Electrically Erasable PROM), an FeRAM (Ferroelectric Random AccessMemory) or an MRAM (Magnetic RAM) or any other suitable kind ofnon-volatile memory.

In the following, a preferred embodiment of the present invention willbe described in greater detail with reference to the accompanyingdrawing figures in which:

FIG. 1 shows a schematic block diagram of a circuit arrangement with aredundancy system according to the preferred embodiment of the presentinvention;

FIG. 2 shows a known circuit arrangement with a redundancy system;

FIG. 3 shows a schematic flow diagram of an initial setting of anon-volatile memory after testing the memory arrangement; and

FIG. 4 shows a schematic flow diagram of a memory error processingmethod according to the preferred embodiment.

The preferred embodiment will now be described based on an errorprocessing circuit arrangement added to a faulty address register aspart of a redundancy system.

FIG. 1 shows the circuit arrangement, wherein a NVE 10 is provided as anon-volatile memory, such as a fuse, antifuse or flash memory or anEPROM (Erasable Programmable Read Only Memory), an EEPROM (ElectricallyErasable PROM), an FeRAM (Ferroelectric Random Access Memory) or an MRAM(Magnetic RAM) or any other suitable kind of non-volatile memory, forstoring a coded faulty-address information of 32 bits to which Nadditional redundant bits have been added for error processing. Thenumber N may be 5, assuming the use of a hamming code for errorcorrection. However, it is noted that any other number N may be usedprovided that an error correction or error detection can be achieved.The NVE 10 is or can be connected to a volatile memory or storage VS 22in which the coded faulty-address information with the N additional bitscan be stored to achieve a fast memory access. The VS 22 is connected toan error processing circuit 24 for performing an error processing byusing the N additional bits for error detection and optional errorcorrection. Furthermore, the coded faulty-address information is decodedto its original size of e.g. 32 bits. Thereby, an error correctedfaulty-address information can be provided.

In case the circuit arrangement is adapted to perform only an errordetection, the error processing circuit 24 may be arranged to output asignal indicating an error, such that a new initialization of the memoryarrangement or another suitable error processing operation can bestarted.

If an error correction processing is provided in the error processingcircuit 24, it can be assured that a correct faulty-address informationis supplied to a subsequent comparison circuit 26 in which thefaulty-address information is compared with an external address A_(ext)according to the known redundancy system as described in connection withFIG. 2, wherein redundancy row signals RR0–RRn are output if an addressmatch is detected.

In general, any type of error correction coding, e.g. hamming codes orparity codes, may be implemented to achieve a redundancy in thefaulty-address information. In case of parity codes, additional paritybits indicating coding errors are provided. Alternatively, if a hammingcode is used, the coded faulty-address information comprises bothaddress bits and check bits. The check bits indicate the correct logicstates of the associated address bits. The error processing circuit 24tests the address bits using the check bits, to generate syndrome bitsindicating which bits in the coded faulty-address information arefaulty. Using the syndrome bits, the error processing circuit 24 maythen correct faulty bits.

FIG. 3 shows a schematic flow diagram of an initial procedure forsetting the non-volatile NVE 10. In step S101, an initial memory testingis performed e.g. after chip manufacturing so as to determine faultymemory cells. The corresponding faulty-address information obtained bythe memory testing in step S101 is read in step S102. Then, an errorcorrection or detection coding is applied in step S103 before the codedfaulty-address information is stored in the non-volatile NVE 10 in stepS104. Thus, a certain amount of redundancy has been added to thefaulty-address information in order to provide an opportunity for latererror detection or error correction.

FIG. 4 shows a schematic flow diagram of an addressing procedure foraddressing the memory of the redundancy system according to thepreferred embodiment.

In an initial initialization step S201, the coded faulty-addressinformation is read from the NVE 10 and stored in the VS 22. Then, thecoded faulty-address information is read from the VS 22 and supplied tothe comparing unit 26 via the error processing or correction circuit 24.At the error processing circuit 24, the coded faulty-address informationis decoded (step S202) and an error correction processing is applied tocorrect any bit error which may have occurred. Then, it is checked instep S203 whether an external address has been received or applied tothe concerned memory. If not, the procedure repeats step S203 until anexternal address has been received.

If an external address has been received, the decoded and correctedfaulty-address information is compared at the comparing circuit 26 withthe external address A_(ext) in step S204. If no address match with oneof the address sections of the faulty-address information is detected instep S205, the external address A_(ext) is supplied to an addressdecoder of the addressed memory in step S206. On the other hand, if anaddress match is detected in step S205, the address decoder isunselected or deactivated in step S207 by issuing a correspondingsignal, and a respective redundancy row is activated by issuing one ofthe signals RR0-RRn in step S208. Finally, the memory access operationis initiated based on the above addressing (step S209). Then, a newaddressing operation may be started e.g. by returning to step S203.

It is noted that the sequence of steps S202 and S203 may be changed ifthe error processing or correction circuit 24 and the comparing unit 26do not include any storing facility for temporary storing the decodingresult or comparing input, respectively. However, in this case, thedecoding and error correction processing has to be repeated each time anew external address is applied.

Thus, an error processing circuit is added in combination with aredundancy system between the VS 22 and the comparing circuit 26 tothereby achieve an error correction or at least an error detection so asto prevent the use of an incorrect faulty-address information. It isnoted, that any coding may be implemented for adding redundancy requiredfor the memory detection or correction. In particular, any redundantcoding scheme for achieving a sufficient hamming distance can beapplied. Consequently, the present invention is not restricted to thepreferred embodiment described above, and can be applied to any memoryarrangement with a redundancy system. The invention is intended to coverany modification within the scope of the attached claims.

1. A method for performing error correction in a memory arrangement,said method comprising the steps of: a) determining a faulty-addressinformation indicating an address of a faulty memory cell of said memoryarrangement; b) adding redundancy by applying a coding to saidfaulty-address information; c) storing said coded faulty-addressinformation; and d) applying an error processing to said codedfaulty-address information before comparing said coded faulty-addressinformation with an address used for addressing said memory arrangement.2. A method according to claim 1, wherein said error processing is anerror correction processing.
 3. A method according to claim 1, whereinsaid coding is an error correction coding.
 4. A method according toclaim 1, wherein said faulty-address information is read from anon-volatile memory (10) and stored in a volatile memory (22) at aninitialization procedure.
 5. A method according to claim 1, wherein saidredundancy is added by adding a predetermined number of error correctioncode bits to said faulty-address information.
 6. A method according toclaim 1, wherein said error processing step comprises a decoding stepfor decoding said coded faulty-address information.
 7. A circuitarrangement for performing an error correction in a memory arrangement,said circuit arrangement comprising: a) storing means (22) far storing acoded faulty-address information indicating an address of a faultymemory cell of said memory information; b) error processing means (24)for applying an error processing to said coded faulty-addressinformation; and c) comparing means (26) for comparing saiderror-processed faulty-address information with an address used foraddressing said memory arrangement.
 8. A circuit arrangement accordingto claim 7, wherein said storing means is a volatile memory (22).
 9. Acircuit arrangement according to claim 8, wherein said volatile memory(22) is a latch, flip flop or SRAM memory.
 10. A circuit arrangementaccording to claim 7, wherein said circuit arrangement is arranged toread said coded faulty-address information from a non-volatile memory(10) at an initialization procedure.
 11. A circuit arrangement accordingto claim 10, wherein said non-volatile memory (10) comprises a fuse,antifuse or flash memory, an EPROM, an EEPROM, an FeRAM or an MRAM. 12.A circuit arrangement according to claim 7, wherein said errorprocessing means (24) is arranged to perform an error correction to saidcoded faulty-address information.